RDF: A Reconfigurable Dataflow Model of Computation

International audienceDataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the first and most popular dataflow MoCs, Synchronous Dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF and most of its variants lack the capability to express the dynamism needed by modern streaming applications. In particular, the applications mentioned above have a strong need for reconfigurability to accommodate changes in the input data, the control objectives, or the environment. We address this need by proposing a new MoC called Reconfigurable Dataflow (RDF). RDF extends SDF with transformation rules that specify how and when the topology and actors of the graph may be reconfigured. Starting from an initial RDF graph and a set of transformation rules, an arbitrary number of new RDF graphs can be generated at runtime. A key feature of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be consistent and live. We introduce the RDF MoC, describe its associated static analyses, and present its implementation and some experimental results

RDF: Un modèle de calcul flot de données reconfigurable

Dataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the first and most popular dataflow MoCs, Synchronous Dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF and most of its variants lacks the capability to express the dynamism needed by modern streaming applications. In particular, the applications mentioned above have a strong need for reconfigurability to accommodate changes in the input data, the control objectives, or the environment. We address this need by proposing a new MoC called Reconfigurable Dataflow (RDF). RDF extends SDF with transformation rules that specify how and when the topology and actors of the graph may be reconfigured. Starting from an initial RDF graph and a set of transformation rules, an arbitrary number of new RDF graphs can be generated at runtime. A key feature of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be consistent and live. We introduce the RDF MoC, describe its associated static analyses, and present its implementation and some experimental results.Les modèles de calcul (MoCs) flot de données synchrones sont très utilisés dans les systèmes embarqués et les applications multimédia, de traitement du signal, de télécommunication et de contrôle automatique. Dans ce style de modèle, une application est spécifiée par un graphe d’acteurs connectés par des liens FIFO de communication. Un des MoCs les plus connus, SDF (pour Synchronous Dataflow), permet des analyses statiques qui garantissent l’exécution en mémoire bornée et l’absence d’interblocage, propriétés clés pour les systèmes embarqués. Néanmoins, SDF (et la plupart de ses variantes) ne permet pas d’exprimer la dynamicité requise par les applications embarquées modernes. En particulier, ces applications ont souvent besoin de se reconfigurer pour s’adapter aux changements (par ex., de débit ou de qualité) du flot d’entrée, des objectifs de contrôle ou de l’environnement. Afin de répondre à ce besoin, nous proposons RDF (pour Reconfigurable DataFlow) un MoC qui étend SDF avec des règles de transformations spécifiant comment la topologie du graphe flot de données peut être reconfiguré dynamiquement. En considérant un graphe SDF initial et un ensemble de règles de transformation, un nombre arbitraire de nouveaux graphes peuvent être produits. La principale qualité de RDF est qu’il peut être analysé statiquement pour garantir que tous les graphes générés dynamiquement s’exécuteront en mémoire bornée et sans interblocage. Nous présentons le modèle RDF, les analyses statiques associées, sa mise en oeuvre et quelques expérimentations

RDF : un modèle flot de données reconfigurable(version étendue)

Dataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the most popular dataflow MoCs, Synchronous Dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF (and most of its variants) lacks the capability to express the dynamism needed by modern streaming applications. In particular, the applications mentioned above have a strong need for reconfigurability to accommodate changes in the input data, the control objectives, or the environment.We address this need by proposing a new MoC called Reconfigurable Dataflow (RDF). RDF extends SDF with transformation rules that specify how the topology and actors of the graph may be reconfigured. Starting from an initial RDF graph and a set of transformation rules, an arbitrary number of new RDF graphs can be generated at runtime. A key feature of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be consistent and live. We introduce the RDF MoC, describe its associated static analyses, and outline its implementation.Les modèles de calcul (MoCs) flot de données synchrones sont très utilisés dans les systèmes embarqués pour les applications multimédia, de traitement du signal, de télécommunication et de contrôle automatique. Dans ce style de modèle, une application est spécifiée par un graphe d’acteurs connectés par des liens FIFO de communication. Un des MoCs les plus connus, SDF (pour Synchronous Dataflow), permet des analyses statiques qui garantissent l’exécution enmémoire bornée et l’absence d’interblocage, propriétés clés pour les systèmes embarqués. Néanmoins, SDF (et la plupart de ses variantes) ne permet pas d’exprimer la dynamicité requise par les applications embarquées modernes. En particulier, ces applications ont souvent besoin de se reconfigurer pour s’adapter aux changements (par ex., de débit ou de qualité) du flot d’entrée, des objectifs de contrôle ou de l’environnement.Afin de répondre à ce besoin, nous proposons le MoC RDF (pour Reconfigurable DataFlow) qui étend SDF avec des règles de transformations spécifiant comment la topologie et les acteurs du graphe peuvent être reconfigurés dynamiquement. En considérant un graphe SDF initial et un ensemble de règles de transformation, un nombre arbitraire de nouveaux graphes peuvent être produits. La principale qualité de RDF est qu’il peut être analysé statiquement pour garantir que tous les graphes générés dynamiquement s’exécuteront en mémoire bornée et sans interblocage.Nous présentons le modèle RDF, décrivons les analyses statiques associées et décrivons brièvementson implémentation

Global Egr1-miRNAs Binding Analysis in PMA-Induced K562 Cells Using ChIP-Seq

Although much is known about microRNAs' regulation in gene expression and their contributions in cell fate, to date, globally lineage-(cell-) specific identification of the binding events between a transcription factor and its targeting microRNA genes is still waiting for elucidation. In this paper, we performed a ChIP-Seq experiment to find the targeting microRNA genes of a transcription factor, Egr1, in human erythroleukemia cell line K562. We found Egr1 binding sites near the promoters of 124 distinct microRNA genes, accounting for about 42% of the miRNAs which have high-confidence predicted promoters (294). We also found EGR1 bind to another 63 pre-miRNAs. We chose 12 of the 187 microRNAs with Egr1 binding sites to perform ChIP-PCR assays and the positive binding signal from ChIP-PCR confirmed the ChIP-Seq results. Our experiments provide the first global binding profile between Egr1 and its targeting microRNA genes in PMA-treated K562 cells, which may facilitate the understanding of pathways controlling microRNA biology in this specific cell line

ATP : une algebre pour la specification et l'analyse des systemes temps reel

This thesis deals with the specification and verification of real time systems. We present an algebra of timed processes ATP for describing such systems using various temporal operators. The operational semantics of ATP is based upon the synchrony hypothesis of the so called synchronous languages. The model associated to a process is a labelled transition system, where the discrete time passing is denoted by a special transition label. A complete axiomatisation of strong equivalence allows to compare two terms without building their models. The algebra's semantics is then generalised to any time domain, and especially to dense time. We show that a safety property is satisfied by a process in any discrete time semantics if it is satisfied in a dense one. In a second part, we study the formalism of timed graphs, which are automata extended with time counters. We present a method for translating ATP into timed graphs, preserving the semantics of processes. The size of the resulting graph is independent from the delay values in the description, since time constraints are expressed symbolically. Finally, we provide an algorithm for verifying properties over timed graphs. It consists in checking a formula of a real time temporal logic using symbolic methods. The main practical interest of this algorithm is to avoid the combinatorial state explosion of the low-level models due to the presence of delay values. We obtain thus the theoretical bases for designing a tool for the description and verification of real time systems. -- Taille du fichier postscript : 1570 KBCe travail porte sur la specification et la verification des systemes temps reel. Nous presentons une algebre de processus temporises ATP, qui permet de decrire de tels systemes en utilisant divers operateurs temporels. Sa semantique operationnelle est basee sur l'hypothese de synchronisme des langages synchrones. Elle definit les modeles des processus comme des systemes de transitions etiquetees, dans lesquels l'evolution discrete du temps est denotee par une etiquette particuliere. Une axiomatisation complete offre la possibilite de comparer deux termes de l'algebre modulo l'equivalence forte sans construire leurs modeles. Nous generalisons ensuite la semantique d'ATP a des domaines temporels quelconques, en particulier des domaines denses. Nous montrons qu'une propriete de surete est satisfaite par un processus pour tout domaine temporel discret si elle l'est pour un domaine dense. Nous etudions dans un deuxieme temps les graphes temporises, qui sont des automates etendus par des compteurs de temps. Nous presentons une methode de traduction d'ATP vers les graphes temporises qui preserve la semantique des processus. Le graphe obtenu presente l'interet d'etre de taille independante des valeurs des delais apparaissant dans la description, car les contraintes temporelles y sont exprimees symboliquement. Finalement, nous decrivons un algorithme de verification de proprietes sur les graphes temporises. Il consiste a evaluer symboliquement des formules d'une logique temporelle temps reel en evitant l'explosion combinatoire du nombre d'etats des modeles de bas niveau causee par les valeurs des delais. Nous obtenons ainsi les principes theoriques d'un outil de description et de verification de systemes temps reel

From ATP to Timed Graphs and Hybrid Systems

The paper presents results of ongoing work aiming at the unification of some behavioral description formalisms for timed systems. We propose for the algebra of timed processes ATP a very general semantics in terms of a time domain. It is then shown how ATP can be translated into a variant of timed graphs. This result allows the application of existing model-checking techniques to ATP. Finally, we propose a notion of hybrid systems as a generalization of timed graphs. Such systems can evolve, either by executing a discrete transition, or by performing some "continuous " transformation. The formalisms studied admit the same class of models: time deterministic and time continuous, possibly infinitely branching transition systems labeled by actions or durations

Symbolic Model Checking for Real-Time Systems

We describe finite-state programs over real-numbered time in a guarded-command language with real-valued clocks or, equivalently, as finite automata with real-valued clocks. Model checking answers the question which states of a real-time program satisfy a branching-time specification (given in an extension of CTL with clock variables). We develop an algorithm that computes this set of states symbolically as a fixpoint of a functional on state predicates, without constructing the state space. For this purpose, we introduce a $\mu$-calculus on computation trees over real-numbered time. Unfortunately, many standard program properties, such as response for all nonzero execution sequences (during which time diverges), cannot be characterized by fixpoints: we show that the expressiveness of the timed $\mu$-calculus is incomparable to the expressiveness of timed CTL. Fortunately, this result does not impair the symbolic verification of "implementable" real-time programs-those whose safety constraints are machine-closed with respect to diverging time and whose fairness constraints are restricted to finite upper bounds on clock values. All timed CTL properties of such programs are shown to be computable as finitely approximable fixpoints in a simple decidable theory

Symbolic Model Checking for Real-time Systems

We describe finite-state programs over real-numbered time in a guarded-command language with real-valued clocks or, equivalently, as finite automata with real-valued clocks. Model checking answers the question which states of a real-time program satisfy a branching-time specification (given in an extension of CTL with clock variables). We develop an algorithm that computes this set of states symbolically as a fixpoint of a functional on state predicates, without constructing the state space. For this purpose, we introduce a -calculus on computation trees over real-numbered time. Unfortunately, many standard program properties, such as response for all nonzeno execution sequences (during which time diverges), cannot be characterized by fixpoints: we show that the expressiveness of the timed -calculus is incomparable to the expressiveness of timed CTL. Fortunately, this result does not impair the symbolic verification of "implementable" real-time programs---those whose safety..